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| SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) Q 6(10) J SUFFIX CERAMIC CASE 620-09 16 1 J 2(14) K 3(13) Q 7(9) 16 1 N SUFFIX PLASTIC CASE 648-08 16 MODE SELECT -- TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load "1" (Set) Hold Toggle Load "0" (Reset) L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H H q q L Q L H H L q q H OUTPUTS 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 5 2 4 3 J SD Q CP KCQ D 1 VCC = PIN 16 GND = PIN 8 11 6 14 J SD Q 12 CP 7 13 KC Q D 15 9 10 * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don't Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the LOW to HIGH clock transition. FAST AND LS TTL DATA 5-1 SN54/74LS109A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S bl Symbol VIH VIL VIK VOH P Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage O Vl 54 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current J, K, Clock Set, Clear J, K, Clock Set, Clear IIL IOS ICC Input LOW Current J, K, Clock Set, Clear Output Short Circuit Current (Note 1) Power Supply Current - 20 0.35 0.5 20 40 0.1 0.2 - 0.4 - 0.8 - 100 8.0 V A 25 2.5 2.7 54 74 - 0.65 35 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 - 1.5 V V V V Typ Max Ui Unit V V T Test C di i Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH MAX, MIN, or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIH mA VCC = MAX, VIN = 7.0 V mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPLH tPHL Parameter P Maximum Clock Frequency Clock Clear Set to Output Clock, Clear, Min 25 Typ 33 13 25 25 40 Max Unit Ui MHz ns ns VCC = 5.0 V 50 CL = 15 pF Test C di i T Conditions AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tW ts th Parameter P Clock High Clear, Set Pulse Width Data Setup Time -- HIGH p Data Setup Time -- LOW Hold time Min 25 20 20 5.0 Typ Max Unit Ui ns ns ns ns VCC = 5 0 V 5.0 Test C di i T Conditions FAST AND LS TTL DATA 5-2 |
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